Increasing I/O Complexity mandates that the I/O Fabric RTL be automatically generated.
As gate count grows the complexity of the I/O integration task is growing and has ended up on the critical path of many chip designs. Spinner is the only EDA tool to specifically address the increasing effort required to integrate the I/O ring.
With increasing I/O layer complexity, SoC pins are heavily bound within a pin-limited package. There is extensive sharing of pins for functional and test purposes. With this growing complexity, the I/O ring is evolving into an I/O fabric that needs to allow full utilization of pin resources and balance constraints from a multitude of sources including functional, DFT, timing, power, die and package constraints.
Bugs cannot be tolerated as a single I/O bug will mandate a complete chip re-spin. As well as causing critical bugs on silicon, I/O bugs in the design process can hinder system-level validation and software integration, fast becoming the critical path for SoC integration.
Spinner is a fully automated solution to manage this increasingly problematic process. Spinner provides an executable specification for the I/O fabric. There are no manual steps from the specification to the generated I/O logic and the generated output is completd validated at all stages.
By automatically generating and validating the I/O fabric from a single executable specification, Spinner can ease SoC I/O integration significantly, potentially providing more than a 20x reduction in effort and more than a 20% reduction in schedule, while at the same time eliminating implementation bugs and keeping the I/O fabric off the critical path.
Using Spinner's Perfect-By-Construction methodology, chip design companies can eliminate bugs, greatly simplify the integration effort and radically improve quality. Spinner has been used on numerous chips to date, including the multimedia processor chip (OMAP) found in the likes of the Nokia N95 smart phone and new Palm Devices.
Many Chip Design companies have developed manual, excel based or semi automated scripted approaches to managing their I/O Layer. These in house methodologies are costly to maintain and more error prone than a commercially available industry standard tool. Take the risk out of the development of your next chip's I/O Layer, let Duolog's award winning Spinner tool automatically deliver it for you. Duolog has considerable expertise and experience in the migration of various data formats into the Spinner tool, allowing immediate customer productivity.
For more information on Spinner, download the Spinner Product Brief or return to the Spinner Product Page.