Webinar: Automating UVM to Tackle Insidious HW/SW Bugs
Date: 11th October 2011 at 9:00 AM PDT / 5:00 PM BST
Location: Online via Registration
This webinar identifies common problems associated with the integration of HW and SW and provides automated solutions to them. All HW/SW systems require multiple teams to agree on interface communications, however, subtle bugs due to miscommunication at the interface can infect the quality of the system especially where false-positive results occur. A combination of advanced verification methodologies such as UVM with formal register management techniques will be shown to eliminate this entire category of bugs from the process. The webinar includes an interactive demo of a complete design and verification environment using Duolog Socrates and Cadence Enterprise Incisive Simulator.