Please register on the registration tab to attend these panel sessions as space is limited.

HW/SW Interface Management – The path to smoother HW/SW integration?

Monday 4^th June, 2:30pm : Duolog Booth # 1520

HW/SW integration is one of the biggest challenges in system realization. The interface between the hardware and software is often the source of issues and inefficiencies that impact productivity, quality and predictability and cause major problems for HW/SW integration. This panel session will discuss the effects of a poorly managed HW/SW interface and explore the types of solutions needed to deliver smoother HW/SW integration. The panel will also consider the outlook for the HW/SW interface and how it might be managed in the future.

Participants:

• Jack Donovan, Duolog Technologies (Moderator)
• Harry Gries, “Harry, the ASIC Guy”.
• Frank Schirrmeister, Cadence Design Systems
• Kurt Shuler, Arteris
• Gary Stringham, Gary Stringham & Associates

SoC Integration – What’s all the fuss about?

Tuesday 5^th June, 2:30pm : ‘The Integration Forum’, Duolog Booth # 1520

Efficient SoC integration is increasingly seen as a key challenge in SoC development. Why is it that the traditional integration flows appear to be failing? At the end of the day, it’s all about stitching a few IPs together, right? So why all the fuss? This panel session will explore how SoC integration has evolved into such a major problem area, as well as investigating the relationship between SoC integration and SoC verification. The discussion will also explore the future trends for SoC integration and how the EDA industry is, or is not, responding to it.

Participants:

• David Murray, Duolog Technologies (Moderator)
• Harry Foster, Mentor
• Paul Martin, ARM
• Warren Stapleton, AMD
• Mike Stellfox, Cadence Design Systems

IP Packaging – What’s in it for me?

Wednesday 6^th June, 2:30pm : ‘The Integration Forum’, Duolog Booth # 1520

The standardization of the different views of an IP has clear benefits for IP integrators but what about the IP developers? Is this simply another burden for IP developers or can standardization be leveraged to enhance IP creation and other flows such as verification, virtual prototyping and software development? This panel will discuss the pros and cons of IP standardization from the perspective of IP providers, IP consumers and EDA developers. The panel will also explore the rate of adoption of the IP-XACT standard and what the future holds for IP-XACT.

Participants:

• Brian Bailey, EE Times (Moderator)
• Grant Martin, Tensilica
• David Murray, Duolog Technologies
• Barry Spotts, Arm
• Adam Traidman, ChipEstimate

Please register on the registration tab to attend these panel sessions as space is limited.

Daily Partner Presentations

Integration, Verification and Software Bring-up of an ARM-based SoC using Duolog Socrates and Mentor Questa

Monday-Wednesday, 11.30am – 12.00pm : ‘The Integration Forum’, Duolog Booth # 1520

In this presentation, we illustrate a holistic integration methodology which creates aligned deliveries for hardware, verification and software teams. Using IP interface standardization and an innovative rules-based integration methodology we show a very quick turnaround time for netlist generation as well as design deliveries for SoC verification and software teams. This presentation includes a demo of the integration, verification and software bring-up of a full ARM-based SoC using Socrates integration platform and Mentor Questa verification platform and IP.

Presenters:

• Jack Donovan/David Murray, Duolog Technologies
• Ellie Burns, Mentor Graphics

Automated IP Creation – Accelerating Virtual Prototype Development using Duolog Socrates and Cadence Virtual System Platform

Monday, 4.00pm – 4.30pm : ‘The Integration Forum’, Duolog Booth # 1520

The formalizing of IP interfaces allows a significant amount of IP collateral to be automated. This presentation focuses on the rapid creation of TLM views of an IP, from a single-source executable specification using Socrates. This presentation also shows how these TLM IP can be easily used to create a virtual prototype within the Cadence Virtual System Platform.

Presenters:

• Jack Donovan, Duolog Technologies
• Larry Melling, Cadence

Formalizing Software Programming Sequences to Accelerate HW/SW Interface Verification using Socrates Sequencer and Cadence Incisive

Tuesday & Wednesday, 4.00pm – 4.30pm: ‘The Integration Forum’, Duolog Booth # 1520

This presentation illustrates how formal programming sequence definition offers the next level of HW/SW interface abstraction. In this presentation we will see how sequences can be defined in a formal manner to become part of a HW/SW interface contract which can be used to automate and guide verification activities. This presentation includes a demo of automating UVM sequences and is demonstrated on the Cadence Incisive Verification Platform.

Presenters:

• Emmett Lee, Duolog Technologies
• Adam Sherer, Cadence

Please complete the form below to register for the DAC2012 Integration Forum panel sessions.

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 HW/SW Interface Management – the path to smoother HW/SW integration?
 SoC Integration – What’s all the fuss about?
 IP Packaging – What’s in it for me?

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