Spinner can add significant value to your design flow through 3 main facets:
- Automation in the design flow
- Quality in the design flow
- A Spinner based methodology is centred on Reuse
Cost Savings
Spinner reduces costs in a number of different ways:
- Spinner fully automates I/O fabric generation which includes a wide range of collateral that is usually captured manually or in a semi-automated way. This includes RTL Logic, I/O Verification infrastructure, documentation, Die/Package specifications, I/O configuration register specifications etc. Incremental changes can be regressed immediately to ensure the I/O fabric is up-to-date.
- Bugs in the I/O layer appear at interfaces between the SoC core, the top-level chip, the system-level testbench and may even involve Software configuration setup. I/O design bugs are costly to find as they can typically block validation. As Spinner includes extensive coherency checks and perfect-by-constructionTM methodology the possibility of propagating a bug through the design flow is essentially eliminated. Manual processes can have 10s to 100s of bugs requiring time to find, fix, validate and synchronise.
- Spinner is centred around a reuse methodology. All of the typical primitives (I/O cells, Power cells, BSR cells etc) used in the I/O fabric are packaged with metadata which can be re-used on multiple projects. These can be stored in IP-XACT format.
In essence, a deployment of Spinner on a single project can reduce spiraling costs significantly.
Schedule Savings
Spinner reduces the number of resources and collapses the scheduled time needed to create the I/O fabric.
- Spinner provides a rich set of time saving features for capturing the I/O fabric. VHDL, Verilog or IPXACT files can be quickly imported and packaged. I/O cells, Core pins and chip pins can be quickly referenced and navigated through in the GUI.
- As Spinner fully automates the I/O fabric, the turn-around-time between a specification change and new RTL generation is minutes.
- With a Perfect-by-constructionTM methodology Spinner eliminates specification and implementation bugs and thus also eliminates time spent being blocked by I/O bugs in the downstream processes.
- The automatic generation of I/O collateral (e.g. Boundary Scan Definition File) used by design flows dependent on the I/O fabric saves time for these teams.
Eliminating Bugs
Spinner eliminates bugs from the I/O Layer. This is a fact proven on each of the chip designs which have utilised Spinner.
- Spinner has a vast array of coherency checks used to ensure a valid and coherent specification. For instance, Spinner will report when a selected I/O cell is not suitable for a given Chip pin.
- The generated fabric may contain specific user defined components and Spinner will analyse the generated fabric to ensure that all ports are connected correctly.
- Rules-based connectivity ensures that I/O connectivity is standardized.
- A comprehensive and extendable self checking test bench ensures full test coverage of all generated I/O Logic.
For more information on Spinner, download the Spinner Product Brief or return to the Spinner Product Page.