Industry Standards
Industry standards allow better design flow interoperability and integration. The EDA tool chain contains a wide variety of language and methodology standards. Duolog is committed to not only targeting these standards but also to supporting and contributing to these standards through our customers and partners’ requirements.
The subset of standards includes:
- IP-XACT
- UVM
- SystemC
IP-XACT
IP-XACT (IEEE-1685), a standard originally progressed by the SPIRIT consortium defines a standard way for describing and handling multi-sourced IP components, enabling automated design integration and configuration within multi-vendor design flows. The IP-XACT standard defines an IP meta-data description in the form of an XML schema. This provides a common and language-neutral way to describe IP that is compatible with automated integration techniques and IP-XACT enabled tools. IP-XACT is now being developed and maintained by Accellera.
Duolog is an associate member of Accellera and has contributed feedback and recommendations since SPIRIT 1.0. Duolog recognizes the immense benefits that a standard such as IP-XACT can bring to SoC developers and IP providers and is fully committed to the IP-XACT standard. Duolog is currently working on IP-XACT 1.6 and also chairing the ‘IP-XACT Best-Practice working group’, in Accellera. All of the tools in the Socrates Integration Platform support IP-XACT, thus providing a standardized interface between Socrates tools and other third-party tools, IPs and flows.
UVM
Universal Verification Methodology (UVM) is a standard methodology developed by Accellera which aims to improve design and verification efficiency, verification data portability and tool/verification IP (VIP) interoperability. Essentially UVM promotes an open, unified class library and methodology for interoperable VIP providing users with advanced verification capability, increased productivity and a high level of interoperability. UVM is a very well supported EDA industry standard.
Duolog has and is continuing to contribute to the development of the UVM standard and further assists UVM users by automating the creation of large parts of the UVM environments. Duolog has used its expertise in register management to help define the UVM register package as well as strengthening the linkage between UVM and IP-XACT. Duolog also provides UVM verification services to develop IP and chip-level verification environments.
SystemC
SystemC refers to the IEEE -1666 standard (1666) which extends the standard C++ language to model system and verification aspects of hardware/software design. SystemC is suited for high-performance reference modeling and transaction level modeling and is generally used in system-level modeling. Leading companies in the semiconductor and embedded software industries currently use SystemC for architectural exploration, to deliver high-performance hardware blocks at various levels of abstraction and to develop virtual platforms for hardware/software co-design. Duolog tools can be used to create SystemC models, in particular Socrates Bitwise can be used to create systemC IP models and Socrates Weaver can be used to create and interconnect SystemC systems.
