Some years ago, Duolog worked with a customer to develop a verification infrastructure for system-level validation of a large multimedia chip. Duolog developed a modular, programmable chip-level testbench, incorporating peripherals, memories, reset, clocks and control. While the delivery of the testbench went well there were some interesting dynamics as the Duolog team as well as software, integration, validation, DFT and IP teams were drawn into an I/O layer heavily infected with I/O bugs that were small, but deadly.