Design & Verification
Duolog provides world-class professional services that utilize our integration expertise to produce high quality, reusable and sustainable solutions. Our services customers achieve schedule predictability to allow their engineering teams to focus on product differentiation rather than product integration.
Duolog addresses the growing quality problem in IP by offering independent high-quality design and verification services to SoC developers and 3rd party IP providers. Our IP verification is built on a stringent process that includes:
- An automated verification infrastructure
- A robust internal and external verification IP
- Advanced verification languages and methodologies
- A process initialized and driven by documented planning
- A tightly integrated and controlled process loop
- Closure gated by a consistent review process
Duolog transforms partially or unverified IP into high-quality verified IP ready for seamless SoC integration with IP-XACT. Solutions include:
- SoC interconnect development and verification
- Legacy IP upgrades
- Self-checking for IP integration
- DFT/STA preparation
The Duolog Difference
The Duolog services team continuously applies new verification methods and processes that capitalize on our EDA tools to successfully achieve shorter verification cycles and allows earlier verification process closure. The close alignment of our services and EDA engineering teams allows us to deliver the best design productivity based on our award-winning Socrates tool suite. The power of Socrates enables automated verification infrastructure and automatic generation of register test cases for large designs with thousands of register addresses.
Our dedicated project management works with your engineering team to deliver personalized status reports and clean interfaces to your managers. We work with all advanced verification languages and methodologies to compliment your solutions.
- USBOTG – Verification of 3rd Party module for USB 3.0 standard. Integrated Verilog testbench into Specman environment. Modeled USB Analog Interface in BFM.
- CAMERA – Validation of mobile subsystem. Developed & integrated PHY VHDL BFM with Specman to handle differential signals. Developed & verified SoC interconnect wrapper for subsystem
- WLAN – Developed SystemC behavioral model for 802.11abg MAC IP with integrated PSL functional coverage. Performed module and system-level verification.
- DISPLAY CONTROLLER – Specman and C based validation of million+ gate sub-system. Integration of IP from multiple sources.
- Scalable ADC – Creation of a configurable testbench in SystemVerilog (UVM) for the purpose of verifying a parameterizable ADC composed of digital and analog (Verilog-AMS) functionality
- HDMI 1.4 – IP integration and Verification based on ‘e’/Specman testbench covering 74 CEA video modes. Development of several checkers and monitors for various IP interfaces.