Weaver- Packaging and Assembly

IP-centric and platform-based methodologies are vital to addressing time-to-market and time-in-market challenges. To support these methodologies, best-practice design flows are enabled by IP standardization, iterative and incremental system integration, a correct-by-construction methodology, and high levels of automation.

WEAVER is an out-of-the box tool that enables such a flow.

WEAVER manages the complete assembly of a complex system from IP to chip-level. Weaver provides design engineers with an efficient platform that enables fast-track integration of components within a complex hierarchical system at IP, sub-system or system-level.

A complex SoC may have hundreds of components and tens of thousands of connections to resolve within an incrementally changing design. Manual assembly is a time-consuming and error-prone activity that is often forced onto the critical path of the design. Automated and formalised assembly and connectivity is essential to an efficient, predictable and robust design flow.

Features

WEAVER has the following high-level features:

• A complete packaging flow that supports the standardization and formalization of IP metadata. This includes the ability to import HDL/IP-XACT interface descriptions and capture additional data and properties
• Rapid sub-system or system assembly using either manual or rules-based workflows
• A coherency checking framework that ensures the correctness of the integrated design
• A generation framework that auto-creates a wide range of outputs including RTL, IP-XACT, verification and documentation views

Check out the complete Weaver Feature Set

Benefits

The main benefits to using WEAVER in your flow include:

• Rapid integration and large-scale automation leads to a significant reduction in integration schedules
• Promotes standardization of IP metadata, ensuring quality, consistency and predictability
• Increased quality, through rules-based and correct-by-construction methodologies, virtually eliminating integration bugs and possible re-spins
• Complete chip integration solution from IP packaging to chip-level assembly
• Supports incremental and iterative design flows with full chip ‘integration synthesis’
• Extensive reuse of both IP data and assembly rules
• Non-disruptive methodology ensures that Weaver slots seamlessly into your existing design flows
• IP-XACT interfaces support interoperability with other IP-XACT-based tools and flows
• Fully Customizable rules allow targeting of key integration activities
• Strong support for NoC-based integration
• Interoperates with other Socrates tools to provide a full chip integration solution in a single platform
• Easy and rapid adoption with powerful and intuitive assembly primitives
• Supports multiple platforms including Windows, Linux & Solaris

To request a quick web-based DEMO or to receive further information, please contact sales@duolog.com

For more information on Weaver, download the Weaver Product Brief