 |
Eliminate I/O bugs, reduce effort, reduce schedule and improve quality by automatically generating your IO fabric. |
With increasing I/O layer complexity, SoC pins are heavily bound within a pin-limited package. There is extensive sharing of pins for functional and test purposes. Bugs cannot be tolerated as a single I/O bug will mandate a complete chip re-spin. With this growing complexity, the I/O ring is evolving into an I/O fabric that needs to allow full utilization of pin resources and balance constraints from a multitude of sources including functional, DFT, timing/power, die and package constraints.
As well as causing critical bugs on silicon, I/O bugs in the design process can hinder system-level validation and software integration, fast becoming the critical path for SoC integration. Spinner is a fully automated solution to manage this increasingly problematic process. By automatically generating and validating the I/O fabric from a single specification, Spinner can ease SoC I/O integration significantly, potentially providing more than 3x reduction in effort and more than 5x reduction in schedule, while at the same time eliminating implementation bugs and keeping the I/O fabric off the critical path.
Using Spinner’s Perfect By Construction methodology, chip design companies can eliminate bugs, greatly simplify the integration effort and radically improve quality. Spinner has been used on over 17 chips to date, including the multimedia processor chip (OMAP) found in the new Nokia N95 smart phone.
Highlights
- Provides a complete I/O solution in a single-source specification which includes features such as functional, DFT, validation and software configuration features
- Proven 3x reduction in SoC I/O integration resources
- Proven 5x reduction in SoC I/O integration schedule
- Removes IO task from integration critical path
- Eliminates SoC IO Bugs with rigorous coherency checks and self-checking test suite
- Immediate turnaround for late I/O Changes
- Fully re-usable methodology - ideal for derivative work
- Flexible and configurable design options to handle complex I/O
- Compatible with your current design flows through standards based interfaces
- Available in several licensing options
- Runs on Windows, Linux and Solaris
With Spinner, the user can define all of the IO layer Interfaces (SoC Core, Die and Packages) as well as IO layer primitives such as IO cells, power cells and DFT cells.These can be defined using the IP-XACT Standard from the SPIRIT consortium. The user can quickly define pin multiplexing scenarios and IO functionality for each of the chip pins as well as allowing complete DFT IO capture, including test multiplexing, enhanced BSR insertion and IO cell control. All information entered can be checked to ensure proper data and functional coherency.
The entire IO fabric can be automatically generated giving a fast turnaround time allowing a sign-off level guarantee on incremental changes. For any SOC development, Spinner eliminates IO bugs and manages the complete IO environment, significantly reducing effort and schedule. For more information on Spinner, download the Spinner Product Brief