I/O layer implementation is a complex task for todays SoCs. The I/O Boundary is where several development disciplines meet and where there are many different requirement scopes. Spinner's feature set offers a solution for the co-ordination, management and delivery of a coherent SoC pin-out.
Spinner manages the resolution of a pin intensive SoC CORE into a pin-limited package automating critical layers of logic into a single robust process. Spinner generates all multiplexing and control logic, BSR ring test logic and power isolation in a highly configurable environment. Spinner also generates a self checking Test-bench that validates all I/O connectivity from core to chip-top.
Spinner Key Features:
- Intuitive GUI and Command Line Interface for specification entry
- Full RTL generation of I/O Fabric
- Full RTL generation of System Test-bench Infrastructure
- Powerful I/O multiplexing
- Extendable self-checking test bench generation
- Automatic test and power isolation logic insertion
- Full support for both Digital and Analog I/O Logic
- Accommodate Hard-Marcos as part of the I/O Logic
- Data coherency checking
- Reusable software configuration
- User defined chip configuration scenarios specification
- Boundary Scan Register Chain Generation
- I/O Cell Daisy Chain Generation
- IP-XACT Support
- Handling of timing critical paths such as clock and reset paths
- Manual Customisation commands allowing any logic creation and connectivity
- Rules Based Customisation commands allowing any logic creation and connectivity
- Customisable I/O Hierarchy
- Custom Generator Framework with full access to the Spinner Data Model
- Extendible Data model
- Runs on Windows, Linux and Solaris
For more information on Spinner, download the Spinner Product Brief or return to the Spinner Product Page.