Bitwise provides a fully automated design view generation and register management capability. It is simple to use and gives immediate benefit by including customizable generators for all the standard design views.
Customizable generators supplied with Bitwise include:
- HTML - web based documentation
- RTF - (MS Word, open office) documentation
- Frame - FrameMaker and Structured FrameMaker documentation
- C - software API
- Cadence Specman - Vr_ad package
- System Verilog - OVM (reg_mem, regdef, .sv)
- System Verilog - description file for Synopsys RAL generator (RALF)
- System C - register models (OSCI with PV SCML)
- Verilog RTL - register & decoder models
- VHDL RTL - register & decoder models