Bitwise - Register Management

Socrates Bitwise manages the HW/SW interface (registers, bitfields, memory maps and memories) and facilitates smooth HW/SW integration. Its correct-by-construction methodology promotes extensive IP reuse, guarantees consistent design views and leads to more right-first-time projects.

Bitwise is a complete register and memory map management tool: Saves time by generating all common design views Increases quality with a vast range of coherency checks Enables reuse of IP, sub-systems or platforms Allows earlier SW integration Fast-tracks IP and SoC system-level validation Immediate turnaround for system changes Flexible and customizable generation framework Complexity-based licensing to suit all design types and sizes

The problem - shorter timescales and larger designs:

As SoC complexity increases and the required time-to-market continues to shorten, the integration of multiple IPs and sub-systems is overloading design and verification flows. The complete software view of an SoC from IP register to full system memory map is typically captured and defined in an ad-hoc manner across document specifications, software libraries and design and verification databases. This leads to inconsistent and out-of-sync information, error-prone and inefficient design flows and, possibly, costly re-spins.

The solution - Bitwise:

Bitwise provides a fully automated solution that allows single-source definition of the HW/SW interface for a full system, leading to earlier software integration, higher productivity, fewer bugs and better communication. Bitwise centres around the three main facets of an automated, correct-by-construction methodology:

• Capture of Hardware/Software interfaces (memory maps and registers)
• Intuitive capture GUI, IP-XACT and Excel import routes
• Data management for easy component re-use and creation of component libraries
• Support for master/slave interfaces, parameterised IP, register arrays, complex access types, multiple operational modes and user-defined properties
• Validation of captured data at both component and system level
• Fast, automatic checking of data for syntax and semantic errors
• Clear problem identification, with click-and-jump to source error.
• Generation of a wide variety of 100% consistent design views
• Fast, automatic generation of consistent design views from one common data source
• Easy to use generator creation and customizable technology
• Supplied with sample generators for all common design flows including HTML, RTF (Word), FrameMaker, Structured FrameMaker, SystemVerilog (OVM , UVM and VMM), Specman 'e' (VR_AD), ANSI C (API), HDL (Verilog and VHDL), System C (PV - SCML)

Through high-levels of automation and perfect-by-construction methodologies, Bitwise has proven a 30x reduction in register and memory map specification and implementation costs. Bitwise has an immediate turnaround time for spec changes and its high-quality outputs facilitate rapid system-level integration which has been proven to deliver a 30% reduction in the full chip design cycle.