Verification Services - Delivering SoC Integration Ready IP
The IP used on today's System-on-Chips (SoC) is increasing in number and complexity. Many IP subsystems currently integrated into SoCs were standalone ICs just a few years ago. The IP on today's SoCs is now obtained from multiple sources including 3rd party IP providers, customer legacy, reuse libraries and newly developed IP.
The uneven quality of this complex and multi-sourced IP is becoming an increasing problem for SoC developers. Recent statistics show that 30-50% of bugs found during top level SoC integration were found in pre-verified IP. Moreover 80% of bugs found at silicon validation were again internal to IP blocks and 14% of failing SoCs had bugs in allegedly silicon proven IP.
Duolog addresses the growing quality problem in IP by offering Independent High Quality IP Verification to SoC Developers and 3rd Party IP Providers. The Duolog solution is built on:
- A Stringent Verification Process
- Automated Verification Infrastructure
- Robust Internal & External Verification IP
- Advanced Verification Languages & Methodologies
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Find information on Duolog Verification IP here.
The Duolog Verification Process
The Duolog verification process consists of 3 components: (1) process management, (2) verification development, and (3) investigation and analysis.
Process Management
Verification Development
At the core of the verification process is the development of the testbench, tests, and coverage. Robust random, coverage-driven and assertion-based verification environments are used for rapid development, debug, and exercising of corner-cases scenarios. Duolog develops synthesisable, eRM compliant, or SystemC/C/C++ based testbenches, and integrates 3rd party IP into existing testbenches. Moreover, test cases are developed that are transaction-based and portable for thorough test coverage, rapid debug, and ease of reuse.
In addition to testbench and test development, Duolog specializes in developing Specman eVCs, SystemC modeling, and synthesisable bus functional models (BFM), which have the added benefit of reuse from simulation to emulation and prototyping.
Investigation and Analysis
Most importantly, the Duolog verification process focuses on investigation and analysis - in other words, finding bugs and measuring quality. Utilising industry leading simulation and debugging tools together with best-in-class methodologies, hard-to-find bugs are quickly isolated and verification closure achieved.
IP readied for SoC Integration
Standalone IP from legacy libraries and 3rd party providers must be readied for SoC integration. Duolog develops and verifies SoC interconnect wrappers for the IP, including assertion based self-checking in the IP to ensure seamless integration. Standalone IP testbenches are integrated or ported to the target verification environment.
In addition, STA and DFT preparation is offered to ensure smooth integration into the target SoC. Duolog delivers verified IP fully packaged for SoC integration and reuse in the future.