Irish EDA startup generates I/O fabrics
By Richard Goering
07/08/08
After winning three "Best of DAC" awards voted by Design Automation Conference attendees, Irish startup Duolog Technologies is bringing its system-on-chip (SoC) integration tools to the North American market. At DAC in June, Duolog announced Spinner, an "I/O fabric synthesis" tool that automatically generates chip I/O layers.
Duolog was the winner of the "most interesting first-time exhibitor" award at DAC, along with "trendsetter" second-place awards for best new product (Spinner) and best demonstration on the exhibit floor. Later in June, Duolog announced a new sales and support office in Los Gatos, Calif., along with plans to enter the Japanese market.
EDA was not Duolog's initial mission. The company was founded in Dublin, Ireland in 1999 with the intent of becoming an IC design services and wireless intellectual property (IP) provider. In 2001 the company provided design services for Texas Instruments' wireless division, and ran into some interesting discoveries, said Dave Murray, Duolog CTO.
"We found very quickly that the biggest bottleneck we were seeing was in the SoC integration phase, where you've got massive libraries of IP and you're trying to get them onto the chip," Murray said. "We started to automate that area and we've been doing that consistently now for about six years."
Initially, Murray said, Duolog design services consultants developed some scripts and Excel spreadsheets that helped automate the SoC integration process. These eventually turned into more sophisticated EDA tools such as Spinner. "After a few years, we realized we were getting more value and revenue from EDA offerings than from IP," Murray said. By 2007, he noted, Duolog decided that its future was in EDA rather than wireless IP.
Duolog doesn't sell IP today but has chosen to retain an IC design services operation based in Budapest, Hungary. "We focus on low cost to help offset Asian challenges, and we think it's a significant differentiator to have IC design engineering in the company," Murray said.
Duolog's stated mission today is "to produce leading edge solutions that allow automation, perfect-by-construction flows, and a high level of collaboration within this design flow." Duolog emphasizes that its tools are designed "by silicon designers for silicon designers."
At present, Murray said, the company is focusing on the integration of IP into systems and subsystems. This includes physical assembly and I/O integration. Spinner, for example, claims to generate a complete I/O layer for an SoC from high-level specifications, and to use a correct-by-construction methodology that includes coherency checking. Along with RTL code, Spinner generates software, documentation, validation, and design for test "views." Duolog also offers Bitwise, which is a register management tool, and OCP [Open Chip Protocol] analysis and debugging tools.
Is Duolog an ESL vendor? "That's a tricky question," Murray said. "We're not focused on the transaction level. The space we're talking about is the lower level of ESL, where we're able to generate a hardware/software interface, and we make sure that RTL and registers can be described at a high level."
Weaving an I/O fabric
Duolog calls Spinner an "I/O fabric synthesis" tool. Why is there a need for automation in this area? "Five or six years ago a single designer could have owned the I/O ring," Murray said. "But what we're seeing now is that the integration task is causing complexity, with more and more things that need to multiplex and share pins. And I/O cells are becoming more and more complex. We see I/O fabrics now with 100,000 gates. That's too much for one person to design and validate."
"I've seen horrendously complex I/O cells that people try to hook up manually," Murray added. "I've seen chips with up to 8,000 components in an I/O layer. Make a mistake on one of them and you're in trouble."
Spinner claims to generate a "complete" I/O fabric, including all logic and wiring for pin muxing, I/O cell control, and boundary scan. It also includes all power isolation logic, all I/O cell instantiation, and custom instances and connectivity. The I/O fabric and the chip top-level routing can be treated as IP deliverables.
Spinner goes further than existing high-level synthesis tools, Murray said. "We have a unique solution in which we treat the pin as a resource you can share and assign to different I/O cells. It's a one-stop solution to your complete I/O layer," he said. In Duolog's view, pins need to be treated as resources that require granular control.
To use Spinner, designers provide specifications through a graphical user interface, or provide IP-XACT schema. Spinner then runs coherency checking on the user input, as well as the RTL that's produced. Spinner produces VHDL or Verilog code for the I/O layer, and can also provide a system-level testbench, since it's generating the top-level chip netlist. Users can also generate documentation, software headers for controlling I/Os, and various pinout scenarios (see Figure 1).
Figure 1 – Spinner generates I/O fabric RTL from high-level specifications.
Duolog claims that Spinner produces much better RTL code than handcrafted code. "There's no comparison," Murray said. "We can have 100,000 lines of VHDL and we're ensuring that there are no errors. We have several layers of optimization, and we optimize for timing."
Bitwise, meanwhile, takes in specifications through a graphical user interface or IP-XACT file. It generates different register "views" including RTL, firmware, and a software API. OCP-Tracker is a system-level tool that provides SoC performance analysis and identifies performance bugs. OCP-Conductor, offered for free, is an SoC transaction analysis and debugging tool.
Gary Johnson, senior vice president of worldwide marketing and sales, is running Duolog's new U.S. office in Los Gatos, Calif. "We want to bring Duolog to the forefront as an interesting new player in this [EDA] area," he said. At present, he acknowledged, Duolog's customers are in Europe, but he believes that will soon change. Johnson noted that Duolog has yet to finalize its U.S. pricing.
How did Duolog get the trendsetter award for best DAC demo? "We did hundreds of demos. We ran our feet off all day long," Murray said. "The people presenting the demos were engineers – we focused on content, not PR." But the giveaways didn't hurt, either. To illustrate SoC integration as the "elephant in the design flow," Duolog gave away stuffed elephants.