This paper describes how that, in order to quickly access these key verification capabilities and apply them to the verification challenges at hand, it is important to automate the creation of as much of the verification infrastructure as possible. A methodology for auto-generating of the OVM IP verification environment, based on the IP interfaces is presented which demonstrates immediate access to correct-by-construction OVM SystemVerilog as well as a tightly integrated Design-Verification view that eliminates synchronization bugs.
The paper shows how 95% of the SystemVerilog environment can be automated and underlines how such a flow allows verification engineers to concentrate on writing verification application code rather than assembling and debugging the verification infrastructure.