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	<title>Duolog Technologies</title>
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	<link>http://www.duolog.com</link>
	<description>Automated Chip Integration</description>
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		<title>DVCon 2012: Duolog will exhibit at Booth #302 the 28-29th February</title>
		<link>http://www.duolog.com/dvcon-2012-duolog-will-exhibit-at-booth-1104-the-28-29th-february/</link>
		<comments>http://www.duolog.com/dvcon-2012-duolog-will-exhibit-at-booth-1104-the-28-29th-february/#comments</comments>
		<pubDate>Tue, 13 Dec 2011 16:21:18 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[David Murray]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[DVCon]]></category>
		<category><![CDATA[IP-XACT]]></category>
		<category><![CDATA[register management]]></category>
		<category><![CDATA[TLM]]></category>
		<category><![CDATA[TLM2.0]]></category>
		<category><![CDATA[UVM]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1766</guid>
		<description><![CDATA[Duolog is exhibiting at DVCon at Booth #302 and presenting "Addressing HW/SW Interface Quality through Standards" on Monday, the 27th February at 3:30.  <a href="http://www.duolog.com/dvcon-2012-duolog-will-exhibit-at-booth-1104-the-28-29th-february/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<p><a href="http://www.duolog.com/wp-content/uploads/2012DVCon_expo.png" rel="shadowbox[sbpost-1766];player=img;"><img class="alignright size-full wp-image-1767" title="2012DVCon_expo" src="http://www.duolog.com/wp-content/uploads/2012DVCon_expo.png" alt="" width="133" height="55" /></a>DVCon 2012 in San Jose, California  &#8211; Exhibiting at Booth #302 from the 28-29th February.</p>
<p>Don&#8217;t miss David Murray, CTO at Duolog Technologies, presenting &#8220;Addressing HW/SW Interface Quality through Standards&#8221; on Monday, the 27th February at 3:30. These standards include IP-XACT, UVM and TLM2.0.</p>
<p>Visit <a title="http://dvcon.org/" href="http://dvcon.org/" target="_blank">here</a> for more details.</p>
]]></content:encoded>
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		<title>Jack Donovan Joins Duolog to Drive Expansion of ESL and TLM Solutions</title>
		<link>http://www.duolog.com/jack-donovan-joins-duolog-to-drive-expansion-of-esl-and-tlm-solutions/</link>
		<comments>http://www.duolog.com/jack-donovan-joins-duolog-to-drive-expansion-of-esl-and-tlm-solutions/#comments</comments>
		<pubDate>Tue, 13 Dec 2011 10:00:41 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Duolog News]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[EDA Tools]]></category>
		<category><![CDATA[ESL]]></category>
		<category><![CDATA[IP integration]]></category>
		<category><![CDATA[Jack Donovan]]></category>
		<category><![CDATA[semiconductor industry]]></category>
		<category><![CDATA[SoC]]></category>
		<category><![CDATA[socrates]]></category>
		<category><![CDATA[system on chip]]></category>
		<category><![CDATA[SystemC]]></category>
		<category><![CDATA[TLM]]></category>
		<category><![CDATA[TLM2.0]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1753</guid>
		<description><![CDATA[DUBLIN, Ireland, December 13th 2011 &#8211; Duolog Technologies, the award-winning developer of IP and SoC integration products, today announced that semiconductor industry veteran and SystemC guru, Jack Donovan, has joined the Duolog team. Based in the company’s Galway, Ireland office, &#8230; <a href="http://www.duolog.com/jack-donovan-joins-duolog-to-drive-expansion-of-esl-and-tlm-solutions/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<p><img class="size-thumbnail wp-image-1763 alignright" title="Jack Donovan, Duolog Technologies" src="http://www.duolog.com/wp-content/uploads/Jack_Donovan6-150x150.jpg" alt="Jack Donovan, Duolog Technologies" width="185" height="185" /></p>
<p>DUBLIN, Ireland, December 13<sup>th</sup> 2011 &#8211; <a href="../../../../../">Duolog Technologies</a>, the award-winning developer of IP and SoC integration products, today announced that semiconductor industry veteran and SystemC guru, Jack Donovan, has joined the Duolog team. Based in the company’s Galway, Ireland office, Donovan will focus on further expanding the capabilities of Duolog’s <em>Socrates</em> tool suite in the ESL and TLM domains.</p>
<p>“Expanding our <em>Socrates</em> tool suite with further ESL and TLM capabilities and applications has become essential as customer demand increases in these areas,” said Ray Bulger, CEO of Duolog Technologies. “Adding somebody of Jack’s calibre to the team will allow us to greatly expand our tools’ capabilities and reinforce our position as one of the leading suppliers of SystemC-based solutions.”</p>
<p>“Duolog’s commitment to extend their SoC integration applications to encompass SystemC and TLM will solidify their position as an EDA pioneer,” said Jack Donovan. “I am excited about joining Duolog and I look forward to working with the Duolog team to deliver innovative solutions to our customers.”</p>
<p>Jack joins Duolog with more than 30 years of experience as a manager and leader of engineering teams. He is a well-known consultant in the EDA industry for his SystemC and TLM 2.0 expertise and is co-author of the industry bestseller, ‘SystemC: From the Ground Up’. Previously, Jack was President and a Member of the Board at XtremeEDA. During his time at XtremeEDA, he Founded ESLX, Inc. and was President before it merged with XtremeEDA. Jack has held various senior management and engineering positions at several companies in San Jose and Austin including Synopsys Inc. and Tandem Computers Jack received his MSEE and BEE from the Georgia Institute of Technology.</p>
<p><strong>About Duolog Technologies: </strong>Duolog Technologies is a leading developer of EDA tools that address the increasingly complex challenges of IP integration. We enable our customers to deliver integrated systems more quickly and cost effectively than their competitors. Our innovative products and solutions allow for maximum productivity and control throughout the entire SoC lifecycle.<strong> </strong></p>
<p>For further information on Duolog, please contact:<br />
Sally Kenny<br />
+353 91 730 879<br />
<a href="mailto:sally.kenny@duolog.com">sally.kenny@duolog.com</a><br />
<a href="../../../../../">http://www.duolog.com</a></p>
<p>Photo compliments of Carol Donovan, <a title="http://www.photoartbycarol.com/" href="http://www.photoartbycarol.com/" target="_blank">www.photoartbycarol.com</a></p>
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		<title>California dreaming for Irish start-ups</title>
		<link>http://www.duolog.com/california-dreaming-for-irish-start-ups/</link>
		<comments>http://www.duolog.com/california-dreaming-for-irish-start-ups/#comments</comments>
		<pubDate>Fri, 02 Dec 2011 13:47:04 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[electronic design automation]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1718</guid>
		<description><![CDATA[The current crop of young companies in Enterprise Ireland’s Silicon Valley company incubator  include Duolog (duolog.com): develops electronic design automation tools for integrating system components on to microchips <a href="http://www.duolog.com/california-dreaming-for-irish-start-ups/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<h3><a title="http://www.irishtimes.com/newspaper/finance/2011/1202/1224308464761.html" href="http://www.irishtimes.com/newspaper/finance/2011/1202/1224308464761.html" target="_blank">Irish Times</a></h3>
<p>By: <a title="http://www.irishtimes.com/newspaper/finance/2011/1202/1224308464761.html" href="http://www.irishtimes.com/newspaper/finance/2011/1202/1224308464761.html" target="_blank">Karlin Lillington</a> December 2nd 2011</p>
<p>For Irish firms ripe for expansion, the Valley is the place to be, writes <strong>KARLIN LILLINGTON</strong> in Silicon Valley</p>
<p>ON THE fourth floor of a building overlooking Castro Street and El Camino in Mountain View, Enterprise Ireland and the Industrial Development Agency face off against each other. On the right side of the hall is the door for IDA Ireland. On the left, Enterprise Ireland, with a little shamrock pasted on to the buzzer.</p>
<p>Beyond the door – one that young Irish companies in Silicon Valley will know well – lies a bright corner suite of rooms that include a series of small offices for the latest group of Irish technology start-ups hoping to crack the US market.</p>
<p>Enterprise Ireland provides working space for companies that are established enough to need a Valley presence, meaning they are beyond the development phase and need a sales and marketing office, says David Ivor Smith, its senior vice-president of telecoms. Along with west-coast office manager Nick Marmion, Smith holds down this Valley fort.</p>
<p>Technology fashions change, and the economic rollercoaster rises and falls, but Enterprise Ireland’s job remains consistent: “We help companies get access but also are serving as a conduit for information,” says Smith.</p>
<p>“The core of what we do hasn’t changed,” says Marmion. “Information gathering, information dispersal. Contacts.”</p>
<p>Government cutbacks in Ireland mean the agency, like other areas of the Civil Service, has had to tighten belts and do more with fewer people, following reductions of about 25 per cent to the agency’s headcount, from 230 to 170. “Yet we have the same number of Irish companies, if not more, to be serviced. So we try to be as lean and efficient as we can,” says Marmion.</p>
<p>New social-media technology tools – including from Irish companies such as DataHug, a recent recipient of Valley venture funding – help maintain and manage networks more easily than in the past, they say.</p>
<p>But Marmion says there’s more money to expand services in some areas, such as bringing Irish companies to exhibit at the likes the upcoming Valley RSA Data Security event; bringing potential buyers of Irish products and services to industry events in Ireland; and funding “pathfinder” visits for companies that need to do market research.</p>
<p>“We’ll be organising an event around the RSA conference, hoping to get 10 companies out, into the marketplace, get some meetings for them. And we’ll have a stand,” says Smith.</p>
<p>Current areas of strength for Irish companies in the Valley include information security, gaming, payments, design innovation, social media and machine-to-machine technology.</p>
<p>A recent survey by the agency identified about two dozen Irish companies in this last area, says Marmion, about twice as many as they’d thought. “It always amazes me, the fertility of Irish companies out there.”</p>
<p>What areas of innovation are big in the Valley? “Think social, local and mobile – ‘SoLoMo’. That’s still really a hot space, as well as the whole idea of hyperlocal: knowing I am walking down Castro Street in Mountain View right now and sending me a coupon for 10 per cent off a pizza, for example. It’s all about . . . analysing big data and personalising it – personalising it down to that person at that time in that space,” says Smith.</p>
<p>But, he adds, areas that garner the most media attention or Valley chat are not typically the areas where the bread-and-butter business is for most companies.</p>
<p>“While Silicon Valley is very much about what’s happening in social media and the different media platforms, ultimately most business is about companies selling within verticals [specific niches and industries],” says Marmion. “So we’re trying to keep a view on . . . what’s emerging and converging, but lots of Irish companies are doing straightforward sales into verticals.”</p>
<p>With few exceptions, most Irish companies in the Valley are “in the commercialisation phase. Sales and marketing are the reasons they’re here,” he says.</p>
<p>Enterprise Ireland doesn’t directly offer incubator space for firms still in the development phase, although there are plenty in the region. “It’s a first sales and marketing foothold in the US that we offer . . . I’d be worried if a company is coming to the Valley from Ireland without a fully developed product,” he says.</p>
<p>Some Irish companies also come looking for Valley venture capital(VC) : “Some more prepared than others,” Marmion says. While there is value to companies in certain sectors to do so (he singles out gaming, which tends to need significant investment and is a hot area for investment), he warns that “companies need to disabuse themselves of the notion that it’s easy to come here and raise money”. “If you haven’t had traction with VCs in Ireland, you’re unlikely to get traction here,” says Smith. “The first thing VCs will ask is why your idea didn’t interest anyone back there,” especially with the increased number of seed funds that involve Valley VCs working with Irish venture funds.</p>
<p>Marmion insists there is funding to be had in Ireland. “While there are clearly banking issues, well thought-out strategy is getting funding.” Irish firms will see increased VC options, he says. To start with, the agency is now seeing a regular influx of Irish VCs to the Valley. Smith has an Irish VC a week coming out for the next couple of months, which is a new development. Some are coming over to talk to Valley VCs, some to look at companies, and some to fundraise.</p>
<p>“Irish VCs are waking up to the idea that they can add value” by working with Valley funds, says, Marmion, and Valley VC firms are increasingly looking towards syndication, setting up branch offices in places like Ireland.</p>
<p>Anything that puts good Irish ideas in front of a range of VCs is a positive development, he says.</p>
<p>Most Irish companies arrive with a greater level of knowledge and understanding of what they need to do than in past years, they say. And compared with a decade ago, there’s a broader, more helpful ecosystem of Irish people working in the Valley who retain strong links with Ireland.</p>
<p>For Irish companies, the pair says – especially the ones ripe for expansion that have won initial business in Ireland, the UK and perhaps Europe, “but aren’t going to scale from Ireland” – it’s a good time to be looking toward the Valley.</p>
<p><strong>HOW GREEN IS THE VALLEY? IRISH SILICON START-UPS IN THE US</strong></p>
<p>The current crop of young companies in Enterprise Ireland’s Silicon Valley company incubator:</p>
<p>Duolog (<a title="http://www.duolog.com/" href="http://www.duolog.com/" target="_blank">duolog.com</a>): develops electronic design automation tools for integrating system components on to microchips</p>
<p>Tethras (tethras.com): provides international language translation to developers for localising apps</p>
<p>Dial2do (dial2do.com): a hands-free service for dialling numbers or speaking messages or tasks to be transcribed and sent</p>
<p>Global Business Register (gbrdirect.eu): sources company information from European official national business registers</p>
<p>TheNowFactory (thenowfactory.com): collects and analyses mobile subscriber data in real time for operators</p>
<p>Seedups (seedups.com): crowd-sources funding for start-ups by connecting companies and investors</p>
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		<title>Duolog IP and SoC Integration Tools Available for Immediate Evaluation via Xuropa</title>
		<link>http://www.duolog.com/duolog-ip-and-soc-integration-tools-available-for-immediate-evaluation-via-xuropa/</link>
		<comments>http://www.duolog.com/duolog-ip-and-soc-integration-tools-available-for-immediate-evaluation-via-xuropa/#comments</comments>
		<pubDate>Tue, 15 Nov 2011 11:57:28 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Duolog News]]></category>
		<category><![CDATA[bitwise]]></category>
		<category><![CDATA[chip I/O]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[EDA Tools]]></category>
		<category><![CDATA[I/O layer]]></category>
		<category><![CDATA[IP integration]]></category>
		<category><![CDATA[register management]]></category>
		<category><![CDATA[SoC]]></category>
		<category><![CDATA[SoC development]]></category>
		<category><![CDATA[SoC Integration]]></category>
		<category><![CDATA[socrates]]></category>
		<category><![CDATA[Socrates Bitwise]]></category>
		<category><![CDATA[Spinner]]></category>
		<category><![CDATA[Weaver]]></category>
		<category><![CDATA[Xuropa]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1695</guid>
		<description><![CDATA[Duolog today announced that both the Socrates Weaver and Socrates Spinner tools are now available for evaluation in the cloud on the Xuropa Cloud Platform.  <a href="http://www.duolog.com/duolog-ip-and-soc-integration-tools-available-for-immediate-evaluation-via-xuropa/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<p>DUBLIN, Ireland, November 15<sup>th</sup> 2011 &#8211; <a href="../../../../../">Duolog Technologies</a>, the award-winning developer of IP and SoC integration EDA tools, today announced that both the <em>Socrates</em> Weaver and <em>Socrates</em> Spinner tools are now available for evaluation in the cloud on the <a title="Socrates Lab" href="http://www.xuropa.com/zone.php?zone_id=117">Xuropa Cloud Platform</a>. Weaver and Spinner join <em>Socrates</em> Bitwise, Duolog’s register and memory-map management tool, in the <a title="Socrates Lab" href="http://www.xuropa.com/zone.php?zone_id=117"><em>Socrates</em> Lab</a> on Xuropa.</p>
<p>“The <em>Socrates</em> Lab on Xuropa puts our tools into the hands of our customers within minutes. This has given users the ability to efficiently evaluate Bitwise from the comfort of their desks,” said Ray Bulger, CEO of Duolog Technologies. “Adding Weaver and Spinner will allow these same users to experience the powerful benefits of our full suite of integration tools.”</p>
<p>The Xuropa platform dramatically simplifies the process of evaluating Duolog’s revolutionary tools. Users with a web browser can test-drive the tools in just minutes, without having to sign any agreements, download software or install license keys.</p>
<p>“Adding a quality tool like Bitwise to Xuropa proved to be extremely beneficial to Duolog, and this was reflected in their sales,” said James Colgan, Founder and CEO of Xuropa. “I am delighted that Duolog has now added the Weaver and Spinner tools to the Lab, and I anticipate a similar sales spike for these products.”</p>
<p>To access the <em>Socrates</em> integration applications, including Bitwise, Weaver and Spinner, simply visit <a title="Socrates Lab" href="http://www.xuropa.com/zone.php?zone_id=117">www.xuropa.com/duolog</a>.</p>
<p><strong>About <em>Socrates</em> Bitwise: </strong>Effective HW/SW integration is one of the biggest challenges facing System-on-Chip (SoC) development teams. Registers and memory-maps are at the heart of the HW/SW interface.  Bitwise manages the entire register and memory-map infrastructure for an IP or system, improving inter-team communications, enhancing design quality and greatly reducing workload.<strong></strong></p>
<p><strong>About <em>Socrates</em> Weaver: </strong>IP reuse and efficient IP integration are essential for successful SoC development. Weaver is a revolutionary tool for IP integration that is the fastest and most efficient way to build and maintain complex systems. The unique rules-based integration methodology employed by Weaver maximizes the potential for IP, subsystem and system reuse.</p>
<p><strong>About <em>Socrates</em> Spinner:</strong> Modern SoC devices typically support multiple static and dynamic operating modes. This can result in thousands of top-level signals that need to be mapped to hundreds of I/O pins, depending on the target application. Spinner manages this increasingly complex area by specifying and auto-generating all of the logic associated with the chip I/O layer.</p>
<p><strong>About Duolog Technologies: </strong>Duolog Technologies is a leading developer of EDA tools that address the increasingly complex challenges of IP integration. We enable our customers to deliver integrated systems more quickly and cost effectively than their competitors. Our innovative products and solutions allow for maximum productivity and control throughout the entire SoC lifecycle.<strong> </strong></p>
<p><strong>About Xuropa Incorporated:</strong> Xuropa is the pioneering cloud demo platform for independent software vendors.  Built upon a unique lead nurturing and analytics engine, Xuropa enables software vendors to conveniently demo their products in the cloud and drive the resultant sales pipeline to increase sales yields.  For more information, go to <a href="http://www.xuropa.com/">http://www.xuropa.com/</a>.</p>
<p>For further information on Duolog, please contact:<br />
Sally Kenny<br />
+353 91 730 879<br />
<a href="mailto:sally.kenny@duolog.com">sally.kenny@duolog.com</a><br />
<a title="http://www.duolog.com/" href="http://www.duolog.com/">http://www.duolog.com</a></p>
<p>For further information on Xuropa, please contact:<br />
James Colgan<br />
+1 415-727-5741<br />
<a href="mailto:sales@xuropa.com">sales@xuropa.com</a><br />
<a href="http://www.xuropa.com/">http://www.xuropa.com</a></p>
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		<title>EDSFair &amp; Embedded Technology 2011: Duolog will exhibit at Booth F-36 the 16-18th November</title>
		<link>http://www.duolog.com/edsfair-embedded-technology-2011/</link>
		<comments>http://www.duolog.com/edsfair-embedded-technology-2011/#comments</comments>
		<pubDate>Tue, 01 Nov 2011 16:50:09 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[EDS Fair]]></category>
		<category><![CDATA[eds fair 2011]]></category>
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		<category><![CDATA[Embedded Technology]]></category>
		<category><![CDATA[Innotech]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=825</guid>
		<description><![CDATA[EDSFair &#038; Embedded Technology 2011 in Yokohama City, Japan – Exhibiting with Innotech on the 16-18th November 2011 <a href="http://www.duolog.com/edsfair-embedded-technology-2011/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<p><a href="http://www.edsfair.com/e/examination/details.php?cd=98&amp;xxx=1319700483" target="_blank"><img class="alignright size-thumbnail wp-image-1568" title="EDSFair 2011" src="http://www.duolog.com/wp-content/uploads/EDSFair-20114-150x150.jpg" alt="EDSFair 2011" width="150" height="150" /></a>EDSFair &amp; Embedded Technology 2011 in Yokohama City, Japan – Exhibiting with <a title="Innotech" href="http://www.innotech.co.jp/english/" target="_blank">Innotech Corporation</a> at booth F-36 from the 16-18th November 2011</p>
<p>Don&#8217;t miss our daily presentation titled: Design and Validation Methods to Improve Quality of the HW/SW interface of an IP using Metadata Management</p>
<p>Visit <a title="edsfair2011" href="http://www.edsfair.com/e/examination/details.php?cd=98&amp;xxx=1319529045" target="_blank">here</a> for more details.</p>
<p>&nbsp;</p>
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		<title>How to Stop “Insidious” Bugs at the HW/SW Interface</title>
		<link>http://www.duolog.com/how-to-stop-%e2%80%9cinsidious%e2%80%9d-bugs-at-the-hwsw-interface/</link>
		<comments>http://www.duolog.com/how-to-stop-%e2%80%9cinsidious%e2%80%9d-bugs-at-the-hwsw-interface/#comments</comments>
		<pubDate>Tue, 01 Nov 2011 08:34:46 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Industry News]]></category>
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		<category><![CDATA[Richard Goering]]></category>
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		<category><![CDATA[UVM]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1637</guid>
		<description><![CDATA[The webinar shows how hardware/software interface bugs arise, how they can be uncovered with help from the Universal Verification Methodology (UVM) register package, and how an automated register management tool can make life even more difficult for HW/SW bugs. <a href="http://www.duolog.com/how-to-stop-%e2%80%9cinsidious%e2%80%9d-bugs-at-the-hwsw-interface/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<h3><a title="http://www.cadence.com/Community/blogs/ii/default.aspx" href="http://www.cadence.com/Community/blogs/ii/default.aspx" target="_blank"><img class="alignright size-thumbnail wp-image-1643" title="SID" src="http://www.duolog.com/wp-content/uploads/SID3-150x150.jpg" alt="" width="150" height="150" />Blog &#8211; Industry Insights</a></h3>
<p>By: <a title="http://www.cadence.com/community/posts/rgoering.aspx" href="http://www.cadence.com/community/posts/rgoering.aspx" target="_blank">Richard Goering</a> October 31st 2011</p>
<p>Meet Sid, the &#8220;insidious&#8221; hardware/software interface bug. He was the star, so to speak, of a recent Duolog Technologies-Cadence webinar now archived at the <a href="../resource-library/webinar-archives/">Duolog web site</a>. The webinar shows how hardware/software interface bugs arise, how they can be uncovered with help from the Universal Verification Methodology (UVM) register package, and how an automated register management tool can make life even more difficult for Sid and his kind.</p>
<p>The webinar is titled &#8220;Automating UVM to Tackle Insidious HW/SW Bugs.&#8221; Presenters are David Murray, Duolog CTO, and Adam Sherer, director of verification solutions at Cadence. Murray kicked off the webinar by noting the importance of concurrent hardware/software development. &#8220;We want to make sure that software can be developed earlier, we want to make sure software is looking at a very accurate model of the hardware, and that we can also allow continuous hardware/software integration on an hourly or daily basis,&#8221; he said.</p>
<p><strong>HW/SW Interface: It&#8217;s Harder Than it Looks</strong></p>
<p>Murray showed a simplified &#8220;programmers view&#8221; of the hardware/software interface, took a deeper look at the IP level, and then showed a diagram of a hardware register that didn&#8217;t look at all simple. &#8220;When you go into a register they are very complex,&#8221; he said. Indeed, there are many attributes associated with registers &#8211; name, register reset, offset, access type, bitfield access, and bitfield reset, to name a few.  A bitfield can have its own reset value and access types. It all adds up to a lot of information that needs to be managed, and that&#8217;s where Sid can easily enter the picture.</p>
<p>&#8220;This [register] structure needs to be understood and implemented in the right way,&#8221; Murray said. &#8220;Someone writes a spec, but the spec can be interpreted and implemented in a variety of different ways. There&#8217;s a lot of duplication of information, a lot of manual processes, and communication between teams starts falling down.&#8221;</p>
<p>It&#8217;s very easy to make a small, subtle error that can cause weeks of effort in the lab. That&#8217;s the nature of an &#8220;insidious&#8221; bug &#8211; &#8220;proceeding in a gradual, subtle way but with harmful effects,&#8221; as Murray said. Dynamics that lead to insidious bugs include incorrect, unclear, or incomplete specifications; errors in translation to an implementation format; and mismatches (lack of synchronization) between different implementations.</p>
<p><strong>UVM to the Rescue</strong></p>
<p>The Accellera UVM 1.0 standard includes a register package, which provides an infrastructure that can verify the hardware/software interface. It comes with pre-packaged test cases, making it very easy to do hardware/software integration testing, Murray said. He walked through a detailed demo that showed UVM working in concert with the Cadence Incisive Enterprise Simulator to track down a bug in which someone changed a reset value without changing the spec.</p>
<p>&#8220;UVM caught the bug,&#8221; Murray noted, &#8220;however, the spec is open to interpretation. There is a possibility we will get symmetrical errors. That means that people designing IP and people verifying IP can make the same mistakes, and it will not appear as an error &#8212; you will get a false positive.&#8221;</p>
<p>Automation is the solution, Murray said, and he discussed the Socrates Bitwise tool from Duolog, which provides a formal, executable specification of the hardware/software interface.  &#8221;When you capture something with a register management tool like Bitwise, the quality of the specification is going to be much better, the interpretation is going to be automatic, and there&#8217;s a correct by construction flow all the way down to implementation.&#8221; In a follow-up demo, Murray showed how UVM in concert with Incisive and Bitwise was able to find an &#8220;insidious bug that was in the background the whole time.&#8221;</p>
<p>Sherer said that Cadence provides a register generation capability for UVM, but Bitwise goes one step further by providing not just generation but static analysis to make sure the specification is captured correctly. &#8220;Customers are working with register environments with hundreds of thousands of register descriptions, far beyond the ability of a human to manage,&#8221; he said. &#8220;I encourage our customers to look at automation for this specification and for UVM, and Duolog is a great choice.&#8221;</p>
<p>The webinar is available <a href="../resource-library/webinar-archives/">here</a>. Registration is required.</p>
<p>Richard Goering</p>
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		<title>Partnership Improves IP-based SoC Assembly</title>
		<link>http://www.duolog.com/partnership-improves-ip-based-soc-assembly/</link>
		<comments>http://www.duolog.com/partnership-improves-ip-based-soc-assembly/#comments</comments>
		<pubDate>Fri, 28 Oct 2011 07:39:01 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Cadence]]></category>
		<category><![CDATA[Cadence Design Systems]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[RTL]]></category>
		<category><![CDATA[SoC]]></category>
		<category><![CDATA[socrates]]></category>
		<category><![CDATA[System Development Suite]]></category>
		<category><![CDATA[TLM]]></category>
		<category><![CDATA[TLM 2.0]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1626</guid>
		<description><![CDATA[Duolog Technologies Ltd has joined forces with Cadence Design Systems Inc. to validate system development flows to RTL SoC assembly. This is made possible by connecting Duolog's integration applications, Socrates, and the Cadence System Development Suite. <a href="http://www.duolog.com/partnership-improves-ip-based-soc-assembly/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<h4>By: <a title="http://www.eetasia.com/ART_8800654501_480100_NP_02d08dda.HTM" href="http://www.eetasia.com/ART_8800654501_480100_NP_02d08dda.HTM" target="_blank">EE Times Asia</a> October 28th 2011</h4>
<p>Duolog Technologies Ltd has joined forces with Cadence Design Systems Inc. to validate system development flows from open, connected and scalable virtual system <a href="http://www.eetasia.com/SEARCH/ART/prototyping.HTM">prototyping</a> connected to RTL <a href="http://www.eetasia.com/SEARCH/ART/SoC+assembly.HTM">SoC assembly</a>. This is made possible by connecting Duolog&#8217;s integration applications, Socrates, and the Cadence System Development Suite.</p>
<p>&#8220;At Duolog, we recognize that a comprehensive data management solution is essential for complex IP-based SoC assembly,&#8221; stated Norman Walsh, COO at Duolog. &#8220;The Cadence System Development Suite provides the key connections between our products to improve team productivity and extend into the vitally important area of <a href="http://www.eetasia.com/SEARCH/ART/software+development.HTM">software development</a>. The collaboration between Cadence and Duolog harnesses the power of our industry-leading Socrates tool suite.&#8221;</p>
<p>&#8220;<a title="Public division belies private cooperation of PCI rivals" href="http://www.eetasia.com/ART_8800240537_590626_NT_2c77e058.HTM">Interoperability</a> with IP-based SoC assembly solutions is an important requirement for improving productivity of system development by enabling earlier software development and rapid system assembly,&#8221; noted Michal Siwinski, product management group director, system and software realization group, Cadence. &#8220;By collaborating with Duolog, we are providing a solution that is open, connected and scalable—essential criteria for developing complex systems in today&#8217;s application-driven technology environment.&#8221;</p>
<p>The Cadence System Development Suite offers four connected platforms that enable hardware-software co-design from early software development to prototyping, while Duolog&#8217;s Socrates manages the assembly of the vital infrastructures of these systems. Socrates assembles the virtual systems, and maintains a consistent HW/SW interface between the virtual and real systems. TLM2.0-based IP can be quickly and easily integrated into virtual systems using the rules-based integration methodology in Socrates.</p>
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		<title>Duolog to Present Revolutionary EDA Tools at MIDAS AGM</title>
		<link>http://www.duolog.com/duolog-to-present-revolutionary-eda-tools-at-midas-agm/</link>
		<comments>http://www.duolog.com/duolog-to-present-revolutionary-eda-tools-at-midas-agm/#comments</comments>
		<pubDate>Tue, 25 Oct 2011 13:29:45 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[EDA Tools]]></category>
		<category><![CDATA[MIDAS]]></category>
		<category><![CDATA[MIDAS AGM]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1675</guid>
		<description><![CDATA[Duolog has been selected to present their award-winning EDA tools at the MIDAS AGM on the 24th November 2011. The event takes place at the Convention Centre in Dublin, Ireland. <a href="http://www.duolog.com/duolog-to-present-revolutionary-eda-tools-at-midas-agm/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<p>Duolog has been selected to present their award-winning EDA tools at the MIDAS AGM on the 24th November 2011. The event takes place at the <a title="http://www.theccd.ie/" href="http://www.theccd.ie/">Convention Centre</a> in Dublin, Ireland.</p>
<p>Visit <a title="http://www.midasireland.ie/" href="http://www.midasireland.ie/" target="_blank">MIDAS</a> for more details.</p>
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		<title>Duolog and Cadence to Validate Interoperability from TLM Virtual Prototype through RTL Assembly</title>
		<link>http://www.duolog.com/duolog-and-cadence-to-validate-interoperability-from-tlm-virtual-prototype-through-rtl-assembly/</link>
		<comments>http://www.duolog.com/duolog-and-cadence-to-validate-interoperability-from-tlm-virtual-prototype-through-rtl-assembly/#comments</comments>
		<pubDate>Mon, 24 Oct 2011 10:00:28 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Duolog News]]></category>
		<category><![CDATA[ARM TechCon]]></category>
		<category><![CDATA[ARM TechCon 2011]]></category>
		<category><![CDATA[Cadence]]></category>
		<category><![CDATA[Cadence System Realization Alliance]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[RTL]]></category>
		<category><![CDATA[RTL Assembly]]></category>
		<category><![CDATA[socrates]]></category>
		<category><![CDATA[Socrates Bitwise]]></category>
		<category><![CDATA[System Realization Alliance]]></category>
		<category><![CDATA[TLM]]></category>
		<category><![CDATA[TLM Flow]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1531</guid>
		<description><![CDATA[Duolog is collaborating with Cadence to validate system development flows to connected RTL SoC assembly. The validated flow connects the Duolog industry-proven integration applications, Socrates, and the Cadence System Development Suite. To further support this flow, Duolog is extending its relationship with Cadence by joining the Cadence System Realization Alliance. <a href="http://www.duolog.com/duolog-and-cadence-to-validate-interoperability-from-tlm-virtual-prototype-through-rtl-assembly/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<p>DUBLIN, Ireland, October 24<sup>th</sup> 2011 &#8211; <a href="../../../../../">Duolog Technologies</a>, the award-winning developer of IP and SoC integration products, is collaborating with Cadence Design Systems to validate system development flows from open, connected, and scalable virtual system prototyping connected to RTL SoC assembly. The validated flow connects the Duolog industry-proven integration applications, <em>Socrates</em>, and the Cadence System Development Suite. To further support this flow, Duolog is extending its relationship with Cadence by joining the Cadence System Realization Alliance.</p>
<p>“At Duolog, we recognize that a comprehensive data management solution is essential for complex IP-based SoC assembly,” said Norman Walsh, Chief Operating Officer at Duolog Technologies.  “The Cadence System Development Suite provides the key connections between our products to improve team productivity, and extend into the vitally important area of software development.  The collaboration between Cadence and Duolog harnesses the power of our industry-leading <em>Socrates</em> tool suite.”</p>
<p>“Interoperability with IP-based SoC assembly solutions is an important requirement for improving productivity of system development by enabling earlier software development and rapid system assembly,” said Michal Siwinski, Product Management Group Director, System &amp; Software Realization Group, Cadence. “By collaborating with Duolog, we are providing a solution that is open, connected and scalable—essential criteria for developing complex systems in today’s application-driven technology environment.”</p>
<p>The Cadence System Development Suite provides four connected platforms that enable hardware-software co-design from early software development through to prototyping, while Duolog’s <em>Socrates</em> manages the assembly of the vital infrastructures of these systems. <em>Socrates</em> assembles the virtual systems, and maintains a consistent HW/SW interface between the virtual and real systems. TLM2.0-based IP can be quickly and easily integrated into virtual systems using the rules-based integration methodology at the heart of <em>Socrates</em>.</p>
<p><strong>Duolog is attending </strong><a href="http://guide.eetimesgroup.com/index.php5?id=198745&amp;fid=5a9103c12c38e9732553776c000235d4&amp;offset=0&amp;highlight=duolog&amp;bc_id=b070862348f1e00c47d91ac17a144fa3&amp;compact=0&amp;tblank=1&amp;path=Home&amp;Action=showCompany">ARM TechCon</a><strong> in Santa Clara, California on October 25<sup>th</sup> (booth #25) to demonstrate their suite of award-winning IP and SoC integration tools.</strong><strong></strong></p>
<p><strong>About Duolog Technologies: </strong>Duolog Technologies is a leading developer of EDA tools that address the increasingly complex challenges of IP integration.  We enable our customers to deliver integrated systems more quickly and cost effectively than their competitors.  Our innovative products and solutions allow for maximum productivity and control throughout the entire SoC lifecycle.<strong> </strong></p>
<p>For further information on Duolog, please contact:<br />
Sally Kenny<br />
+353-91-730 879<br />
<a href="mailto:sally.kenny@duolog.com">sally.kenny@duolog.com</a></p>
<p><a href="../../../../../">http://www.duolog.com</a></p>
<p>&nbsp;</p>
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		<title>Duolog to Present IP-XACT Solution to Increase IP Quality through Register Management at ARM TechCon</title>
		<link>http://www.duolog.com/duolog-to-present-ip-xact-solution-to-increase-ip-quality-through-register-management-at-arm-techcon/</link>
		<comments>http://www.duolog.com/duolog-to-present-ip-xact-solution-to-increase-ip-quality-through-register-management-at-arm-techcon/#comments</comments>
		<pubDate>Tue, 18 Oct 2011 14:00:55 +0000</pubDate>
		<dc:creator>duolog</dc:creator>
				<category><![CDATA[Duolog News]]></category>
		<category><![CDATA[ARM Duolog]]></category>
		<category><![CDATA[ARM TechCon]]></category>
		<category><![CDATA[ARM TechCon 2011]]></category>
		<category><![CDATA[Duolog]]></category>
		<category><![CDATA[Duolog Socrates]]></category>
		<category><![CDATA[Duolog Technologies]]></category>
		<category><![CDATA[IP-XACT]]></category>
		<category><![CDATA[register management]]></category>
		<category><![CDATA[socrates]]></category>
		<category><![CDATA[Socrates Bitwise]]></category>

		<guid isPermaLink="false">http://www.duolog.com/?p=1515</guid>
		<description><![CDATA[Duolog is exhibiting and presenting at ARM TechCon 2011. The technical paper presents an IP-XACT solution to increase IP quality through register management. <a href="http://www.duolog.com/duolog-to-present-ip-xact-solution-to-increase-ip-quality-through-register-management-at-arm-techcon/">Learn more <span class="meta-nav">&#8594;</span></a>]]></description>
			<content:encoded><![CDATA[<p>DUBLIN, Ireland, October 18<sup>th</sup>, 2011 &#8211; <a href="../../../../../">Duolog Technologies</a>, the award-winning developer of IP and SoC integration products, has been selected to present a technical paper at <a href="http://guide.eetimesgroup.com/index.php5?id=198745&amp;highlight=&amp;compact=0&amp;fid=d9d774f77ca3a870fd96b383900f7a39&amp;offset=0&amp;sfr=1&amp;bc_id=78dafad9b896e023a62352d84776ce55&amp;tblank=1&amp;Action=showCompany">ARM TechCon</a>.  The presentation highlights how Duolog’s <em>Socrates</em> integration applications interoperate with Cadence Incisive Enterprise Simulator products to demonstrate register management as a fully mature IP methodology.  Duolog will present this solution during ARM TechCon in Santa Clara on Tuesday, 25<sup>th</sup> October at 11:00 a.m. PDT.</p>
<p>“Improving IP quality is essential, especially for streamlining hardware/software integration,” said David Murray, Duolog’s CTO and featured ARM TechCon speaker. “The presentation illustrates a sample flow that shows how IP-XACT can be used as an interoperable register specification to save development time and effort and increase design quality.”</p>
<p>The technical paper, titled “Increasing IP Quality through Register Management using Cadence Incisive” explores the types of quality issues that are typical on the HW/SW interface of an IP.  A complete register management solution is presented with auto-generated outputs including VHDL, Verilog, SystemC and SystemVerilog, and supporting methodologies such as TLM2.0, UVM and CMSIS.  The solution features Duolog’s industry-leading register and memory-map management tool, <a href="../../../../../products/bitwise/"><em>Socrates</em> Bitwise</a>.</p>
<p>Duolog will also be exhibiting at ARM TechCon on Tuesday, 25<sup>th</sup> October in <a href="http://guide.eetimesgroup.com/index.php5?id=198745&amp;highlight=&amp;compact=0&amp;fid=d9d774f77ca3a870fd96b383900f7a39&amp;offset=0&amp;sfr=1&amp;bc_id=78dafad9b896e023a62352d84776ce55&amp;tblank=1&amp;Action=showCompany">Booth #25</a>. The Duolog team will be demonstrating their industry-leading <em>Socrates</em> tool suite. In addition, Duolog have successfully collaborated with ARM to present, “Faster Fabric Integration using ARM CoreLink™ AMBA® Designer &amp; Duolog <em>Socrates</em>” at the Duolog booth. The presentation focuses on the complementary benefits of combining <em>Socrates</em> with ARM’s system IP and CoreLink™ AMBA® Designer. This results in faster and more consistent IP integration and system assembly with fewer bugs and reduced verification times.</p>
<p><strong>About Duolog Technologies: </strong>Duolog Technologies is a leading developer of EDA tools that address the increasingly complex challenges of IP integration.  We enable our customers to deliver integrated systems more quickly and cost effectively than their competitors.  Our innovative products and solutions allow for maximum productivity and control throughout the entire system lifecycle.<strong> </strong></p>
<p><em>Cadence is the  registered trademark of Cadence Design Systems, Inc. in the United States and other countries.</em></p>
<p>For further information on Duolog, please contact:<br />
Sally Kenny<br />
+353-91-730 879<br />
<a href="mailto:sally.kenny@duolog.com">sally.kenny@duolog.com</a></p>
<p><a href="../../../../../">www.duolog.com</a></p>
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