Sequences: Formalizing software programming sequences to enhance HW/SW integration

CDNLive! EMEA, Wednesday 16th May 2012, 11.30am : SDV06, System Realization – Design & Verification

Hardware and Software engineering teams utilise different development environments and are often geographically dispersed. They typically rely upon paper-based design specifications to describe their shared interface which is often incomplete or ambiguous.

In order to accurately describe the HW/SW interface it is necessary to document: the structure of the registers; the mapping of the register set into an addressable memory map; the constraints which describe the allowed value ranges for registers and the data dependencies between registers. Also a programmer’s guide will typically contain the programming sequences required to perform certain IP functions.

Commercial register definition tools exist today to simplify the capture of the structure and mapping of registers. This single source specification ensures consistency between the hardware-firmware and design-verification teams through the automated generation of the output they need in their flows. The benefits of this type of approach are well understood in the industry and has been formalised in standards like IEEE-1685. Also advanced verification methodologies such as UVM have also defined and simplified registers structures to allow more efficient verification of the HW.SW interface.

However, to date, architects and IP designers have not had a way to formally and precisely capture the programming sequences needed to fully describe HW/SW interfaces. This presentation outlines a methodology of defining these essential sequences using a sequence specification language and defines programming sequences as a series of register accesses to configure an IP block. This methodology uses a C-based sequence specification language with close linkage to formal register data such as IP-XACT. This presentation illustrates how these sequences can be used to generate documentation, verification test-cases and software setup routines and deliver major improvements in HW/SW integration productivity, quality and predictability.

Check back here, after the 16th May, for the slides…

Advanced Verification Techniques for the Mixed-Signal Domain

CDNLive! EMEA, Wednesday 16th May 2012, 11.00am : FV11, Silicon Realization Functional Verification

Over the past decades, complexity and quality requirements for digital designs have continually expanded and driven the need for new and improved verification technologies such as functional coverage, constrained-random verification and object-oriented languages. The Mixed-Signal design verification flow is now reaching an inflection point at which traditional methodologies are no longer viable; leveraging proven digital verification flows to improve verification of Mixed-Signal designs is therefore an increasingly attractive option. Coupling this proven advance verification methodologies with the top down analog design approach allows verification of mixed combinations of RTL, gate level, Verilog-AMS or transistor level delivering a powerfull framework for design exploration and system validation.

This paper describes how a SystemVerilog-based Universal Verification Methodology (UVM) testbench is developed and used to verify a mixed-signal design. Analog cells are initially developed in Verilog-AMS and used later to validate the transistor level implementations. The testbench is self-checking and designed for randomized coverage-driven verification which supports different levels of analog modeling from Verilog-AMS to circuit-level. In addition, the paper addresses the trade-off decisions taken while developing analog models in Verilog-AMS as well as the calibration work conducted to ensure circuit-level implementations and models match. SystemVerilog assertions are used to monitor correct interconnection between analog and digital domains.

Check back here, after the 16th May, for the slides…

Rapid IP-Centric Virtual Prototype Development

This presentation introduces an IP model development methodology allowing a high level of automation producing significant proportions of RTL and TLM implementations from a single source description.This methodology relies on a formal definition of IP metadata describing HW/SW interfaces and wrappers for TLM/RTL hybrid integration. The result of this methodology includes the creation of TLM (SystemC or SystemVerilog) and RTL code from a single source with a high percentage of automatically generated code and enabling much earlier software development.
Read More …

Addressing HW/SW Interface Quality through Standards

As software is an increasingly important aspect of system development, product schedules are mandating the earlier development of software concurrently with hardware. The Hardware/Software (HW/SW) interface is a critical development artifact that plays a key role in efficient system realization.

This white paper gives an overview of the HW/SW interface and discusses the typical complexities encountered when designing the SW/HW interactions. The HW/SW interface flow is analyzed to show how insidious bugs are introduced into this domain. A compelling HW/SW interface solution is presented that combines best-practice design, formal specifications, the leveraging of different industry standards and register management solutions.

Read More …

• Rapid IP Integration using rules-based system assembly and connectivity
• Comprehensive IP HW/SW integration and verification using UVM
• Formal programming sequence definition

Duolog is presenting two papers at CDNLive. Don’t miss David Murray, CTO Duolog, presenting:

Sequences: Formalizing software programming sequences to enhance HW/SW integration, learn more

Wednesday, 14th May : 11.30 am : SDV06 – System Realization Design & Verification

Fergal Strumble, Verification Services Project Manager, is presenting:

Advanced Verification Techniques for the Mixed-Signal Domain, learn more

Wednesday, 14th May : 11.00 am : FV11 – Silicon Realization Functional Verification

Users with a web browser can test-drive Duolog’s revolutionary System-on-Chip integration tools in minutes. To access Duolog’s freely available OCP toolkit and also the Socrates integration applications, simply visit the Socrates Lab on Xuropa. Once engineers have utilized the OCP toolkit, they can then request a free members’ copy via the OCP-IP website.

“Adding the OCP toolkit to the Socrates Lab on Xuropa demonstrates Duolog’s continued commitment to OCP-IP users. The toolkit, which is free for OCP-IP members, allows users to track and tune the performance of their system’s OCP infrastructure,” said Ray Bulger, CEO of Duolog Technologies. “In addition to immediately accessing the OCP toolkit, visitors to the Socrates lab can also try out Socrates Weaver, which offers the fastest, most efficient and reusable methodology for OCP integration and system assembly.”

“Duolog Technologies has been a long-standing contributing member to the OCP international partnership, and I am pleased that they have made their OCP toolkit more accessible to OCP users,” said Ian Mackintosh, president and chairman of OCP-IP. ”Duolog continues to support OCP users by providing a pre-configured library of OCP integration rules as part of its Socrates Weaver system integration tool.”

About OCP Tracker: OCP Tracker allows designers of OCP-based systems to tune their architectures to maximize performance. It provides graphical, statistical and transaction analysis of OCP interfaces and fabrics. It also enables validation of performance metrics via a built-in regression manager and seamlessly interfaces with OCP-IP’s CoreCreator II trace files to allow bandwidth, latency and other types of performance metrics to be analyzed. OCP Tracker’s 3D 360° navigation engine allows these metrics to be visualized in an intuitive way. It provides an understanding of how OCP systems cope with different types of traffic patterns, thus enabling the identification of the optimal architectural structure of the SoC.

About OCP Conductor: OCP Conductor is an innovative, detailed OCP transaction viewer that enables fine-grained analysis of bus transactions. A complete transaction sequence can be traced from request to response along with a host of related information about the transaction, permitting instant, powerful, high-level OCP transaction analysis and debug. Transactions are visually extracted from simulations and presented in a user-friendly and intuitive way.

About Duolog Technologies: Duolog Technologies is a leading developer of EDA tools and solutions that address the increasingly complex challenges of IP integration. We enable our customers to deliver integrated systems more quickly and cost-effectively than their competitors. Our innovative products and solutions allow for maximum productivity and control throughout the entire SoC lifecycle.

About OCP-IP: Formed in 2001, OCP-IP is a non-profit corporation promoting, supporting and delivering the only openly licensed, core-centric protocol comprehensively fulfilling integration requirements of heterogeneous multicore systems. The Open Core Protocol (OCP) facilitates IP core reusability and reduces design time, risk, and manufacturing costs for all SoC and electronic designs by providing a comprehensive supporting infrastructure. For additional background and membership information, visit www.ocpip.org.

About Xuropa Incorporated: Xuropa is the pioneering cloud demo platform for independent software vendors. Built upon a unique lead nurturing and analytics engine, Xuropa enables software vendors to conveniently demo their products in the cloud and drive the resultant sales pipeline to increase sales yields. For more information, go to www.xuropa.com.

For further information on Duolog, please contact:
Norman Walsh
+353 1 217 8400
info@duolog.com
http://www.duolog.com

For further information on OCP-IP, please contact:
Joe Basques
+ 1 512-551-3377
joe@ocpip.org
http://www.ocp-ip.org

For further information on Xuropa, please contact:
James Colgan
+1 415-727-5741
sales@xuropa.com
http://www.xuropa.com

• Rapid IP Integration using rules-based system assembly and connectivity
• Comprehensive HW/SW Integration solutions utilizing standards such as UVM
• Fast Integration of your I/O Layer
• A sneak preview into the future of formal programming sequence definition

Don’t miss Jack Donovan, a TLM industry expert, presenting at CDNLive:

Rapid IP-Centric Virtual Prototype Development

Wednesday, the 14th March : 11 am : Track Six – System/ Software/ IC Packaging

As Software development has become the key enabler for application-enabled platforms it has also become the dominant cost, schedule and resource factor in system realization. Software critical path mitigation requires earlier development of software artifacts and mandates early and accurate models of the hardware platform.

Hardware platform development is increasingly focused around integrating configurable IP around a proven core system leading semiconductor companies taking on the role of ‘integrators’. IP components therefore need to be developed concurrently with the software and provide early and accurate models for software development. As with most critical paths, the challenge is how to provide these model as early as possible and SystemC TLM2.0 allows modeling of a system at a higher level of abstraction allowing faster model development than the hardware counterpart and also allow faster simulation speeds for efficient software debug. Because the HW/SW interface is critical to the whole software development cycle, it is necessary to ensure IP models are register-accurate. The rapid integration of these IP into a system is also vital to earlier software development and integration, the system typically being a mix of different levels of abstraction.

This presentation presents an IP model development methodology which allows a high level of automation that produces significant proportions of RTL and TLM model implementation from a single source description. This methodology relies on formal definition of IP metadata, including the HW/SW interface that allows automated creation of RTL, TLM IP implementations. The methodology can also automate the creation of IP wrappers to enable both RTL and TLM hybrid IP integration

The presentation also introduces an single source RTL/TLM ‘flick switch’ connectivity solution that automates the creation of system level connectivity models at either the RTL or TLM abstraction level with the ability to switch from one to the other – at the flick of a switch.

Finally a complete flow is presented from IP level packaging and TLM model creation, through automated RTL and TLM abstracted (flick-switch) system connectivity, to compilation and simulation in the Cadence VSP environment

Blog – Integration Insights : SID at DVCON2012

By: David Murray February 24th 2010

Yes : SID is still around!  SID is the ‘Insidious Bug’ that creeps around the front-end of the design flow.  He lives in incomplete or ambiguous specifications. He thrives on misinterpretation.  He lurks in parts of the design flow where design intent is heavily shared between different teams, and he is subtle and sneaky – but when he strikes it’s with very painful consequences.

If you want to find out all about SID then come along to my DVCON presentation : Addressing HW/SW Interface Quality Through Standards, Wednesday 29^th Feb : 9:30 am : Room: San Jose/Santa Clara Room

Also, on the Monday I am presenting as part of the IP-XACT TC Tutorial on IP-XACT and UVM Monday 27^th Feb : 4:30pm-5:00pm : Room : Pine Ballroom.

And if you miss these two, then call around to the Duolog Booth #302 anytime on Tuesday, February 28 – 3:30-6:30pm, or Wednesday, February 29 – 4:30-7:00pm where we can show you our latest SoC integration technologies.

• Rapid IP Integration using rules-based system assembly and connectivity
• Comprehensive HW/SW Integration solutions utilizing standards such as UVM
• Fast Integration of your I/O Layer
• A sneak preview into the future of formal programming sequence definition

• Rapid IP Integration using rules-based system assembly and connectivity
• Comprehensive HW/SW Integration solutions utilizing standards such as UVM
• Fast Integration of your I/O Layer
• A sneak preview into the future of formal programming sequence definition

Don’t miss David Murray, CTO at Duolog Technologies, presenting at DVCon:

IP-XACT Tutorial – IP-XACT and UVM

Monday, the 27th February : 4.30pm : Room Pine Ballroom

IP-XACT can be used to describe many aspects of the HW/SW Interface. This presentation explains the IP-XACT HW/SW Interface constructs that can be used to allow automation of the UVM register packages. Its shows how this automation enables a very efficient HW/SW Interface verification flow using UVM.

White Paper: “Addressing HW/SW Interface Quality through Standards”

Wednesday, the 29th February at 9.30am : Room San Jose/Santa Clara

This white paper and presentation details the types of quality issues faced during HW/SW Integration. It explains how the use of standards such as IP-XACT, UVM, TLM2.0 and CMSIS, together with proven register management techniques, provides dramatic increases in quality. The presentation also discusses where the next level of standardization is happening in the HW/SW Interface and profiles some of the emerging solutions.

Visit here for more details.

DUBLIN, Ireland, December 13^th 2011 – Duolog Technologies, the award-winning developer of IP and SoC integration products, today announced that semiconductor industry veteran and SystemC guru, Jack Donovan, has joined the Duolog team. Based in the company’s Galway, Ireland office, Donovan will focus on further expanding the capabilities of Duolog’s Socrates tool suite in the ESL and TLM domains.

“Expanding our Socrates tool suite with further ESL and TLM capabilities and applications has become essential as customer demand increases in these areas,” said Ray Bulger, CEO of Duolog Technologies. “Adding somebody of Jack’s calibre to the team will allow us to greatly expand our tools’ capabilities and reinforce our position as one of the leading suppliers of SystemC-based solutions.”

“Duolog’s commitment to extend their SoC integration applications to encompass SystemC and TLM will solidify their position as an EDA pioneer,” said Jack Donovan. “I am excited about joining Duolog and I look forward to working with the Duolog team to deliver innovative solutions to our customers.”

Jack joins Duolog with more than 30 years of experience as a manager and leader of engineering teams. He is a well-known consultant in the EDA industry for his SystemC and TLM 2.0 expertise and is co-author of the industry bestseller, ‘SystemC: From the Ground Up’. Previously, Jack was President and a Member of the Board at XtremeEDA. During his time at XtremeEDA, he Founded ESLX, Inc. and was President before it merged with XtremeEDA. Jack has held various senior management and engineering positions at several companies in San Jose and Austin including Synopsys Inc. and Tandem Computers Jack received his MSEE and BEE from the Georgia Institute of Technology.

About Duolog Technologies: Duolog Technologies is a leading developer of EDA tools that address the increasingly complex challenges of IP integration. We enable our customers to deliver integrated systems more quickly and cost effectively than their competitors. Our innovative products and solutions allow for maximum productivity and control throughout the entire SoC lifecycle. 

For further information on Duolog, please contact:
Sally Kenny
+353 91 730 879
sally.kenny@duolog.com
http://www.duolog.com

Photo compliments of Carol Donovan, www.photoartbycarol.com