Duolog is Exhibiting at the 49th Design Automation Conference (DAC) San Francisco CA, June 3-7
Duolog Technologies will be exhibiting at 49th Annual Design Automation Conference (DAC) San Francisco CA, June 3-7. Visit Us at Booth #1520 where we will show case our latest SoC Integration and Verification technologies.
SOC Integration and Verification
Duolog is a pioneering developer of EDA solutions that enable rapid and error-free SoC integration. Duolog’s Socrates integration platform is a correct-by-construction environment for IP, subsystem and system-level integration. Socrates supports current and emerging standards such as IP-XACT and UVM, and auto-generates synchronized views for ESL, hardware, verification and software teams. Socrates delivers major benefits to Duolog’s customers – eliminating bugs, shrinking design cycles and greatly enhancing inter-team communications.
The Integration Forum
Duolog will be hosting a series of panel sessions in conjunction with leading industry experts at the ‘The Integration Forum‘ theatre beside Duolog’s Booth #1520.
Learn more about these panel sessions and be sure to register as space is limited.
Time |
Panel Session |
| Mon 4th June, 2:30pm | HW/SW Interface Management – The path to smoother HW/SW integration? |
| Tues 5th June, 2:30pm | SoC Integration – What’s all the fuss about? |
| Wed 6th June, 2:30pm | IP Packaging – What’s in it for me? |
Partner Presentations
Joint partner presentations with Cadence and Mentor Graphics will demonstrate highly integrated flows for SoC integration and verification at the ‘The Integration Forum‘ theatre beside Duolog’s Booth #1520.
Learn more about these partner presentations.
Time |
Partner Presentation |
| Monday-Wednesday, 11.30am – 12.00pm | Integration, Verification and Software Bring-up of an ARM-based SoC using Duolog Socrates and Mentor Questa |
| Monday, 4.00pm – 4.30pm | Automated IP Creation – Accelerating Virtual Prototype Development using Duolog Socrates and Cadence Virtual System Platform |
| Tuesday & Wednesday, 4.00pm – 4.30pm | Automated IP Creation – Accelerating Virtual Prototype Development using Duolog Socrates and Cadence Incisive |
