Duolog will be presenting "Auto-Generation of an OVM IP verification infrastructure" at the OVM world booth in DAC on Tuesday 28th @11am.
Abstract
The increasing size and complexity of today’s Systems-on-Chip is driving the adoption of modular, IP-centric design and verification flows. Increasingly complex IPs, sub-systems and systems require high levels of modularization, standardization and re-use and must be comprehensively verified as quickly and efficiently as possible. Advanced verification methodologies such as OVM provide important verification capabilities such as coverage-driven verification and reusable verification components, while leveraging the benefits of object-oriented development. The presentation describes how that in order to quickly access these key verification capabilities and apply them to the verification challenges at hand, it is important to automate the creation of as much of the verification infrastructure as possible. The presentation outlines a methodology for auto-generating much of the OVM verification environment for an IP from an interface-based specification and demonstrates how IP verification engineers can gain immediate access to OVM as well as a tightly integrated Design-Verification view that eliminates synchronization bugs. The presentation concludes with how this flow allows verification engineers to concentrate on writing verification application code rather than assembling and debugging the verification infrastructure.
'OVM World' is located in Booth # 3450. Check out http://www.ovmworld.org/tradeshows.php