High Quality. Advanced Methods. Proven Track Record
- IP Module development from Specification to STA
- Block/IP level verification, sub-system and SoC verification in ‘e’/Specman or SystemVerilog with methodologies such as eRM or UVM
- Execution of coverage driven functional verification with tailored processes that promote integration with Client product development processes
- Development of complete verification environments and VIPs for automotive, mobile & consumer
- Secure work environment: client audited offices, with option of secured closed room, equipped with security system specified by majority of Fortune-100 Companies
Client Success Stories
IP integration and Verification based on Specman e testbench covering 74 CEA video modes. Development of several checkers and monitors for various IP interfaces.
Creation of a configurable testbench in SystemVerilog (UVM) for the purpose of verifying a parameterizable ADC composed of digital and analog (Verilog-AMS) functionality.
Specman and C based validation of million+ gate sub-system. Integration of IP from multiple sources.
Developed SystemC behavioral model for 802.11abg MAC IP with integrated PSL functional coverage. Performed module and system-level verification.
Validation of mobile subsystem. Developed & integrated PHY VHDL BFM with Specman to handle differential signals. Developed & verified SoC interconnect wrapper for subsystem.
Verification of 3rd Party module for USB 3.0 standard. Integrated Verilog testbench into Specman environment. Modeled USB Analog Interface in BFM.